1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and semiconductor memory circuit suitable for facilitating a diagnostic test for product inspection by changing a pulse width and a timing sequence of an internal activation signal which controls the active/inactive operations of an internal circuit.
2. Description of the Related Art
A dynamic-type semiconductor integrated circuit has an internal circuit controlled by an internal activation signal (hereinafter also referred to just as an activation signal). FIG. 24, shows a schematic diagram of a conventional dynamic-type semiconductor integrated circuit. In FIG. 24, xe2x80x9cL1xe2x80x9d to xe2x80x9cLmxe2x80x9d indicate internal circuits, xe2x80x9cCK1xe2x80x9d to xe2x80x9cCKmxe2x80x9d indicate activation signals, and xe2x80x9cMPCxe2x80x9d indicates an activation signal generator comprising a plurality of pulse control circuits PC1 to PCm. xe2x80x9cCKEXxe2x80x9d indicates a reference signal, e.g., an external clock signal.
The dynamic-type semiconductor integrated circuit is advantageous over a static-type semiconductor integrated circuit in that a beta ratio of the internal circuits L1 to Lm (a ratio of a beta factor of a P-type MOS transistor to a beta factor of an N-type MOS transistor) is increased, such as by a higher-speed operation. In a static semiconductor memory cell and a current-mirror sense amplifier, power is consumed only during an active period, i.e., no power is consumed during an inactive period. This feature provides an advantage of reducing power consumption.
FIG. 25 shows a detailed arrangement of the activation signal generator MPC in a conventional dynamic-type semiconductor integrated circuit. In FIG. 25, xe2x80x9cMPCxe2x80x9d indicates the entire activation signal generator, and xe2x80x9cPC1xe2x80x9d indicates a pulse width shortener for keeping the pulse widths of the activation signals CK1 to CKm constant. The pulse width shortener PC1 comprises a delay circuit DL10 and a NOR circuit N10. In the pulse control circuit PC2, there are delay circuits DL20 and DL21, and in the pulse control circuit PCm, there is a delay circuit DLm. The activation signals CK1 to CKm are generated with reference to the external clock signal CKEX. On a signal line S10 in the activation signal generator MPC, the polarity of the external clock signal CKEX is reversed. A test mode signal TM and an external input signal EXT are explained later.
FIG. 26 shows a timing chart of the external clock signal CKEX and other signals. Through the pulse width shortener PC1, the activation signal CK1 is a signal which goes to a high potential level only when both the external clock signal CKEX and its inverted signal S10 are at a low potential level. In other words, the pulse width (tw1) of the activation signal CK1 is narrower than the pulse width (twck) of the external clock signal CKEX, and the pulse width (tw1) of the activation signal CK1 is constant (i.e., invariable with the time length of an operation cycle since the delay circuit DL10 provides a constant delay time td10). A timing point t2 of the activation signal CK2 is set according to a delay time (td20) of the delay circuit DL20 or a delay time (td21) of the delay circuit DL21, and a timing point tm of the activation signal CKm is set according to a delay time (tdm0) of the delay circuit DLm0.
A diagnostic test (normal operation test, or IDDQ test) and a failure analysis to be performed during a semiconductor integrated circuit inspection are described as follows. In the normal operation test, an output signal resulted from the execution of an input signal sequence is monitored to determine a GOOD/NO GOOD condition. In the IDDQ test, a power supply current is monitored when an internal node is in a completely quiescent state (pause phase), and a GOOD/NO GOOD condition is determined according to the magnitude of the power supply current. Since to the IDDQ test does not require propagating a fault indication in an internal node to an output pin, the IDDQ test is regarded as a rather direct diagnostic test. However, both of the normal operation test and the IDDQ test require carrying out a plurality of input signal sequences for checking all the concerned internal nodes.
Regarding the failure analysis, there is a well-known method in which an output signal of a semiconductor integrated circuit is monitored and analyzed with a logic tester (or memory tester). Alternatively, an internal signal is observed and analyzed with a probe or an electron beam tester. These failure analysis methods, however, require a relatively long time to identify a fault location. Therefore, recently, another failure analysis method called a light detection test, has become popular. In the light detection test, a fault location is identified by detecting the heat caused by a leak current at a fault location. The light detection test is particularly advantageous in that it takes relatively short time to identify a fault location.
Another diagnostic test or failure analysis method employs a technique of externally controlling the timing of activation signals which is disclosed in U.S. Pat. No. 5,270,977. This technique uses the pulse control circuit PC2 of the activation signal generator MPC shown in FIG. 25. The pulse control circuit PC2 is provided with two operation modes: a normal operation mode and a test mode. The switch between these modes is controlled by the test mode signal TM. In the normal operation mode, the delay circuit DL20 is used for controlling of the activation signal CK2. In the test mode, the delay circuit DL21 is used for controlling the timing of the activation signal CK2. The external input terminal EXT of the delay circuit DL21 receives an external signal supplied through an external pin of the semiconductor integrated circuit. In other words, with the external signal supplied from a tester through the external pin, the timing of the activation signal CK2 is adjusted with the tester. This technique, for example, can judge whether or not a malfunction in the normal operation mode is caused by any insufficiency of the timing margin of the activation signal CK2.
In a dynamic-type semiconductor integrated circuit, however, it is difficult to carry out the IDDQ test or the light detection test under the required conditions. More specifically, as shown in the signal timing chart in FIG. 26, the pulse width corresponding to an evaluation period is constant and narrow for each of the activation signals CK1 to CKm. Therefore, during the evaluation period, it is difficult to provide a pause phase of the internal node, which results in an inadequate condition for the IDDQ test. Further, even if there is a leak current fault, there usually is not sufficient heat for identifying the fault location, which makes it impracticable to carry out the light detection test. In contrast, the pulse width corresponding to a precharge period can be widened by increasing the time length of an operation cycle. Therefore, during the precharge period, a pause phase of the internal node can be provided for executing the IDDQ test. For example, immediately before the end of each operation cycle, the IDDQ test is carried out as indicated by the pulse form of an IDDQ signal in FIG. 26. In addition, if a leak current fault occurs during the precharge period, sufficient heat can be attained for identifying a fault location so as to execute the light detection test.
Satisfactory diagnosis cannot be performed in the IDDQ test and the light detection test, since adequate conditions are not provided during the evaluation period as mentioned above, although it is allowed to conduct diagnosis satisfactorily during the precharge period.
Further, in an initial trial production stage process conditions are not yet stable, a margin of timing between an input signal to an internal circuit and an activation signal tends to be insufficient to cause a malfunction, which results in additional complication in identifying a cause and a location of a fault. In other words, it becomes difficult to determine whether the malfunction is caused by an insufficient timing margin or by a leak current in the internal circuit. Therefore, for ensuring satisfactory accuracy in diagnosis, it is also important to eliminate any insufficiency in timing margin.
The U.S. Pat. No. 5,270,977 also discloses a technique for determining whether a malfunction is caused by an insufficient timing margin or not. However, this conventional technique is not designed for the IDDQ test and light detection test in cases where the pulse width of each activation signal is as narrow as noted above.
It is therefore an object of the present invention to provide a dynamic-type semiconductor integrated circuit wherein an IDDQ test and a light detection test are performed under adequate conditions during an evaluation period for diagnosis and failure analysis with improved accuracy.
In accomplishing this object of the present invention and according to one aspect of the invention, a dynamic-type semiconductor integrated circuit is provided with a normal operation mode and a test mode, wherein the switch therebetween is performed by a mode selection signal. In the normal operation mode, the pulse width of an internal activation signal is controlled to be constant, i.e., invariable with an operation cycle time length. In the test mode, the pulse width of the internal activation signal is controlled to vary depending on an operation cycle time length. Thus, a pause phase of an internal node is provided during an evaluation period so as to carry out satisfactory diagnosis and failure analysis.
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description with reference to the accompanying drawings.